Advanced HDL synthesis and SOC prototyping RTL design using verilog

Advanced HDL synthesis and SOC prototyping RTL design using verilog

Bibliographic Details
Main Author: Taraate, Vaibbhav (Author)
Corporate Author: SpringerLink (Online service)
Format: Electronic Resource
Language:English
Published: Singapore Springer [2019]
Edition:First edition.
Subjects:
Electronic circuits.
Logic design.
Microprogramming.
Electronic books.
Online Access:Available for University of the Philippines Diliman via SpringerLink. Click here to access
Also available remotely for University of the Philippines Diliman via SpringerLink. Click here to access thru EZproxy