Showing
1 - 7
results of
7
for search '
'
Skip to content
UPFind
Book Bag:
0
items
(Full)
Language
English
Deutsch
Español
Français
Italiano
日本語
Nederlands
Português
Português (Brasil)
中文(简体)
中文(繁體)
Türkçe
עברית
Gaeilge
Cymraeg
Ελληνικά
Català
Euskara
Русский
Čeština
Suomi
Svenska
polski
Dansk
slovenščina
اللغة العربية
বাংলা
Galego
Tiếng Việt
Hrvatski
हिंदी
All Fields
Title
Author
Subject
Call Number
ISBN/ISSN
Find
Advanced
Page will reload when a filter is removed.
Applied Filters:
SUBJECT:
Remove Filter
Cache memory
Page will reload when a filter is removed.
Show filters (1)
SUBJECT:
Remove Filter
Cache memory
Search Results
Showing
1 - 7
results of
7
for search '
'
, query time: 0.05s
Refine Results
Sort
Relevance
Newest to Oldest
Oldest to Newest
Author
Title
Select Page
Email
Export
Print
Add to Book Bag
Select result number 1
1
Less-reused filtering and live time prediction in multi-core processors with a shared L2 cache
by
Dioquino, Darryl Aldrin M.
Published 2013
Call Number:
loading...
Located:
loading...
Thesis
loading...
Add to Book Bag
Remove from Book Bag
Select result number 2
2
A study of snoopy cache coherence protocols for dual processor systems
by
Fernandez, Edward Bryann C.
Published 2007
Call Number:
loading...
Located:
loading...
Thesis
loading...
Add to Book Bag
Remove from Book Bag
Select result number 3
3
The Cache-coherence problem in shared-memory multiprocessors hardware solutions
Published 1993
Call Number:
loading...
Located:
loading...
Book
loading...
Add to Book Bag
Remove from Book Bag
Select result number 4
4
Cache and interconnect architectures in multiprocessors
Published 1990
Call Number:
loading...
Located:
loading...
Book
loading...
Add to Book Bag
Remove from Book Bag
Select result number 5
5
Implementation of a 32-bit dual core ARM7 microprocessor with split-private level one cache and shared level two data cache
by
Alidio, Lianne
Call Number:
loading...
Located:
loading...
Thesis
loading...
Add to Book Bag
Remove from Book Bag
Select result number 6
6
A study of cache sub-ranking and block buffering as power reduction techniques for multiprocessor cache design
by
Zarsuela, Jestoni V.
Call Number:
loading...
Located:
loading...
Thesis
loading...
Add to Book Bag
Remove from Book Bag
Select result number 7
7
RT-CaCC towards a cache-aware congestion control mechanism in wireless sensor networks
by
Alipio, Melchizedek I.
Call Number:
loading...
Located:
loading...
Thesis
loading...
Add to Book Bag
Remove from Book Bag
Select Page
Email
Export
Print
Add to Book Bag
Search Tools:
Email Search
Back
Refine Results
Page will reload when a filter is selected or excluded.
CAMPUS
Diliman
7 results
7
DATABASE
Union Catalog (Buklod)
7 results
7
UNIT LIBRARY
College of Engineering Library II
7 results
7
Main Library: University Archives
2 results
2
YEAR OF PUBLICATION
From:
To:
CLASSIFICATION
L - Education
5 results
5
Q - Science
1 results
1
T - Technology
1 results
1
SUBJECT
Cache memory
Multiprocessors
3 results
3
Computer architecture
1 results
1
Computer network architectures
1 results
1
Computer network protocols
1 results
1
Congresses
1 results
1
Electric power consumption
1 results
1
Multiprogramming (Electronic computers)
1 results
1
RISC microprocessors
1 results
1
VHDL (Computer hardware description language)
1 results
1
Wireless sensor networks
1 results
1
see all…
AUTHOR
Alidio, Lianne
1 results
1
Alipio, Melchizedek I.
1 results
1
Dioquino, Darryl Aldrin M.
1 results
1
Dubois, Michel, 1953-
1 results
1
Fernandez, Edward Bryann C.
1 results
1
Fernandez, Jose Luis
1 results
1
Montes, Julie Ann Gaspara
1 results
1
Palma, Camille Mary Joyce
1 results
1
Thakkar, S. S.
1 results
1
Tiglao, Nestor Michael C.
1 results
1
Zarsuela, Jestoni V.
1 results
1
see all…
RESOURCE TYPE
Thesis
5 results
5
Book
2 results
2
LANGUAGE
English
7 results
7
TUKLAS
: UP Libraries' Resource Discovery Tool
Copyright © 2020-2021. The University Library, University of the Philippines Diliman