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  1. 1

    A practitioner's guide to RISC microprocessor architecture by Stakem, Patrick H.

    Published 1996
    Book


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  2. 2

    C compiler back end for the 32-bit dual core capable DLX microprocessor by Ostrea, Allan Michael M.

    Published 2007
    Thesis


    Cover Image
  3. 3

    Compiler implementation for the dual-core ARM7 microprocessor by Delas Alas, Jerome

    Thesis


    Cover Image
  4. 4

    An asynchronous implementation of a 32-bit DLX microprocessor by Dumaguing, Christian Loyd G.

    Thesis


    Cover Image
  5. 5

    Implementation of a 32-bit dual core ARM7 microprocessor with split-private level one cache and shared level two data cache by Alidio, Lianne

    Thesis


    Cover Image
  6. 6

    Power optimization of the ARM7TDMI-S Microprocessor in 90nm CMOS process by Dimanarig, Angelo Dilla

    Thesis


    Cover Image
  7. 7

    High-Level Implementation of the 5-Stage Pipelined ARM9TDM Core by Arandilla, Christiensen dela Cruz

    Thesis


    Cover Image
  8. 8

    A study of selective power-down techniques for low-power RISC microprocessor design by Khalid, Sihawi Abdulhamid

    Published 2004
    Thesis


    Cover Image
  9. 9

    Design and implementation of a 32-Bit dual core capable DLX microprocessor with single-level cache by Dioquino, Darryl Aldrin M.

    Published 2007
    Thesis


    Cover Image
  10. 10

    DLXPlus a DLX processor simulator with memory subsystem by Diaz, Michelle A.

    Thesis


    Cover Image

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